Analytical Modeling and Simulation of Short-channel Effects in a Fully Depleted Dual-material Gate (dmg) Soi Mosfet

Silicon-on-insulator (SOI) has been the forerunner of the CMOS technology in the last decade offering superior CMOS devices with higher speed, higher density, excellent radiation hardness and reduced second order effects for submicron VLSI applications. Recent experimental studies have invigorated interest in fully depleted (FD) SOI devices because of their potentially superior scalability relative to bulk silicon CMOS devices. Many novel device structures have been reported in literature to address the challenge of short-channel effects (SCE) and higher performance for deep submicron VLSI integration. However, most of the proposed structures do not offer simultaneous SCE suppression and improved circuit performance. Others involve complicated processing not amenable for easy integration into the present CMOS technology. Dual-Material Gate (DMG) structure offers an alternative way of simultaneous SCE suppression and improved device performance by careful control of the material workfunction and length of the laterally amalgamated gate materials. A physics based analytical model of surface potential along the channel in a FD DMG SOI MOSFET is developed by solving 2-D Poisson’s equation. The model is used to investigate the excellent immunity against SCE offered by the DMG structure. Further the model is used to formulate an analytical expression of the threshold voltage, Vth. The results clearly demonstrate the scaling potential of DMG SOI devices with a desirable threshold voltage “roll-up” observed with decreasing channel lengths. Numerical simulation studies were used to explore and compare the novel attributes of DMG SOI MOSFET with a conventional single-material gate (SMG) device in terms of circuit parameters like transconductance, drain conductance, voltage gain, leakage current, on-current and Vth “roll-up”. An optimum gate length ratio of the two gate lengths, L1/L2 = 1, and a workfunction difference, ∆W = 0.4 eV, between them workfunctions is pointed by the simulation studies. In conclusion, we have demonstrated the superior attributes offered by the DMG structure in FD SOI devices by developing a simple analytical model and extensive simulation studies. The results presented in this work are expected to provide incentive for further experimental exploration.